Integrated circuits are mass produced by fabricating hundreds of identical circuit patterns on a single semiconductor wafer. One of the many different processes repeated repeatedly in manufacturing these integrated circuits is that of using a mask and etchant for forming a particular feature. In such a mask and etching process, a photo mask containing the pattern of the structure to be fabricated is created, then, after formation of a material layer within which the feature is to be formed, the material layer is coated with a light-sensitive material called photoresist or resist. The resist-coated material layer is exposed to ultraviolet light through the mask, thereby transferring the pattern from the mask to the resist. The wafer is etched to remove the material layer unprotected by the resist, and then the remaining resist is stripped. This masking process permits specific areas of the material layer to be formed to meet the desired device design requirements.
In the etching process described above, it may be important that the etching selectively remove the unwanted material and that the material underlying the material layer is not significantly altered. A common way to accomplish this is to deposit or otherwise form an etch-stop layer on the wafer prior to formation of the material layer to be etched. Such etch-stop layers are commonly made of a material that is resistant to the particular etching process used for the overlying material layer. In such a case, the etch process is said to be “selective” to the etch-stop layer.
The connections between the transistors in a semiconductor device are referred in the art as interconnects. When copper is used as the interconnect conductor, the copper features may be defined using the damascene process. In this process, material is removed from the dielectric used in the interconnect level in the pattern of the desired copper features, after which these areas of removed dielectric are filled with copper. Removal of the dielectric material is typically done using an etch process utilizing a plasma.
The damascene process may use an etch-stop layer under the dielectric layer being patterned. When it is used, it is prior to filling the patterned features with copper to allow electrical connection between multiple levels of the integrated circuit. Removal of the etch-stop layer can be done by either an ex-situ or in-situ process.
An ex-situ etch-stop etch process is one in which the dielectric etch is done, and chamber vacuum is broken before the etch-stop etch is done. Moreover, the substrate may be removed from the chamber, and the etch-stop etch process may be performed as another process step, perhaps in another plasma reactor. There may optionally be processing steps separating the two etch processes, such as a cleaning process to remove photoresist and etch residue. An in-situ etch-stop etch process is one in which the etch-stop etch is performed in the same plasma tool as the dielectric etch, without breaking vacuum. The in-situ etch-stop etch allows processing steps to be eliminated, reducing manufacturing costs.
One disadvantageous result of using an in-situ etch process is that etch residues, referred to as “polymer,” produced during the trench or via etch process, are not removed prior to the etch-stop etch. When the etch-stop layer overlies a metal level, the opening in the dielectric generally overlies copper structures in the lower interconnect level. When copper is exposed during the etch-stop etch process, copper can be sputtered onto the polymer on the walls of the opening. When copper is sputtered onto the polymer, the resulting residue can be difficult to remove in subsequent cleanup steps, and may result in increased particle defects on the semiconductor substrate. Furthermore, the presence of polymer in the bottom of the trench or via opening decreases the uniformity of the thickness of the combined etch-stop layer and polymer, requiring a longer over-etch at the end of the etch-stop etch process. The longer over-etch exacerbates the copper sputtering by leaving copper exposed to the plasma for a longer period on some areas of the wafer. The combination of these effects leads to lower product yield and higher manufacturing costs per finished unit.
In order to address the above cited deficiencies in the art, what is needed in the semiconductor art is an in-situ etch-stop etch process that results in lower polymer formation.